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商品編號:
DOD1737
商品名稱:
Actel Libero IDE v8.3 Windows
語系版本:
英文正式版
運行平台:
WIN9x/WINME/WINNT/WIN2000/WINXP/WIN2003
更新日期:
2008-05-25
碟片數量:
1片
銷售價格:
200
瀏覽次數:
7579
熱門標籤:

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Actel Libero IDE v8.3 Windows
Actel Libero IDE v8.3 Windows 英文正式版(DVD版)


破解說明:
Check Readme.txt into Shooters Dir
內容說明:
Actel's Flagship FPGA Development Software Libero Integrated Design
Environment (IDE) is Actel's comprehensive software toolset for designing
with all Actel FPGAs. From schematic and/or HDL design, synthesis and
simulation, through floorplanning, place-and-route, timing constraints and
analysis, power analysis, and program file generation, Libero IDE manages
the entire design flow quickly and efficiently.

Libero IDE provides full power optimization and analysis tools for Actel's
low-power flash FPGA families, including IGLOO and ProASIC3L, the latest
addition to the ProASIC3 family. Product Features and Types Libero IDE
offers the latest and best-in-class FPGA development tools from leading
EDA vendors such as Mentor Graphics, SynaptiCAD, and Synplicity. These tools,
combined with Actel developed tools allow you to quickly and easily manage
your Actel FPGA designs. An intuitive user interface and powerful design
manager guides you through the process while organizing design files and
seamlessly managing exchanges between the various tools.

Libero IDE Software Features:

- Powerful project and design flow management
- Full suite of integrated design entry tools and methodologies:
- CoreConsole subsystem creation
- Core Catalog and Configuration
- ViewDraw Schematic Capture
- SmartDesign graphical block subsystem creation with automatic HDL
abstraction
- HDL and HDL templates
- "User-defined blocks" creation flow for design re-use
- Actel macro cells
- Synplify/Synplify Pro AE synthesis fully optimizes Actel FPGA device
performance and area utilization
- Synplify DSP AE performs high-level DSP optimizations within a Simulink
environment
- Test-bench generation including analog stimulus via WaveFormer Lite AE.
Advanced analog stimulus functionality is available from SynaptiCad.
- ModelSim VHDL or Verilog behavioral, post-synthesis and post-layout
simulation capability
- Designer physical design implementation, floorplanning, physical
constraints, and layout
- Timing- and power-driven place-and-route
- SmartTime environment for timing constraint management and analysis
- SmartPower provides comprehensive power analysis
- Interface to FlashPro and Silicon Sculptor programming software
- Identify AE debugging software for Actel flash designs
- Silicon Explorer debugging software for Actel antifuse designs
- Supported on Windows and Linux operating systems
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